In the last fifteen years, the practice of synthesizing hardware from software descriptions has grown from a simple idea to a practical reality. Today, commercial systems permit the designer to construct high-level specifications in graphical or textual form; these descriptions are then ``compiled'' into hardware. This technology opens up new opportunities for the application of customized hardware, by broadening the community of people who can specify hardware and by extending the capacity of those people already doing it. Unfortunately, the commercial systems for ``compiling'' hardware description languages lack many of the improvements that have been developed over the last forty years for ``software'' compilers. We sought to apply the insights derived in classic scalar compiler research to the problems of compiling hardware description languages by building an optimizer for one of the intermediate formats used in compiling the VHDL hardware description language.
This research was funded by DARPA.